1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device that is incorporated in a portion of a semiconductor integrated circuit in which a plurality of first power source lines to which a first voltage is applied and a plurality of second power source lines to which a second voltage is applied are arranged in a lattice.
2. Description of the Background Art
FIG. 15 is a diagram showing the configuration of a conventionally common semiconductor chip. A semiconductor chip 1000 shown in FIG. 15 has a six-layered line structure, and includes a sixth layer VSS power source line (hereinafter, referred to as “M6VSS line”) 1001, a sixth layer VDD power source line (hereinafter, referred to as “M6VDD line”) 1002, a fifth layer VSS power source line (hereinafter, referred to as “M5VSS line”) 1003, a fifth layer VDD power source line (hereinafter, referred to as “M5VDD line”) 1004, a memory circuit 1005, a logic circuit 1006, a logic circuit 1007, and a functional block circuit 1008. The black circles in FIG. 15 denote contacts. The memory circuit 1005, the logic circuit 1006, the logic circuit 1007, and the functional block circuit 1008 are collectively called “a semiconductor device”. The M5VSS line 1003, the M5VDD line 1004, the M6VSS line 1001, and the M6VDD line 1002 are collectively called “power source lines in the fifth and sixth layers”.
The semiconductor device is formed from the first to the fourth layers. The M5VSS line 1003 and the M5VDD line 1004 are basically arranged alternately in the fifth layer while extending in the column direction. The M6VSS line 1001 and the M6VDD line 1002 are basically arranged alternately in the sixth layer while extending in the row direction. The M6VSS line 1001 and the M5VSS line 1003 supply a ground voltage VSS to the semiconductor chip 1000. The M6VDD line 1002 and the M5VDD line 1004 supply a power source voltage VDD to the semiconductor chip 1000. In the semiconductor chip 1000 shown in FIG. 15, the semiconductor device formed in the fourth layer and the layers beneath is designed, and then the power source lines in the fifth and sixth layers are designed.
In recent years, libraries of circuits including a semiconductor device and a portion of power source lines (hereinafter, referred to as “modules”) are created in order to facilitate the design of a semiconductor chip. In a circuit design using modules from circuit libraries, modules of a plurality of patterns that are designed in advance are combined so that a semiconductor chip is designed. Hereinafter, a circuit library of modules will be described with reference to the accompanying drawings. FIG. 16 is a diagram showing the configuration of a module including a memory circuit as an example of the module from circuit libraries.
The module shown in FIG. 16 is a circuit designed from the first layer to sixth layer, and includes a memory circuit 1005, an M6VSS line 1011, an M6VDD line 1012, an M5VSS line 1013, and an M5VDD line 1014. In circuit design using modules from circuit libraries, a plurality of module as shown in FIG. 16 are arranged. Thereafter, power source lines for connecting power source lines between the plurality of modules are arranged. In this manner, a semiconductor chip is designed. Thus, using modules from circuit libraries, it is not necessary to design each module from the scratch, and thus the design of a semiconductor chip is facilitated.
However, in the circuit design using modules from circuit libraries, it is necessary to design the power source lines in the fifth and sixth layers in accordance with the arrangement of the modules. Hereinafter, this problem will be described with reference to the accompanying drawing. FIG. 17 is a diagram showing the state in which the module shown in FIG. 16 is connected to power source lines around the periphery of this module.
Since the module is a circuit that is designed in advance, the power source lines included in the module are arranged with a predetermined gap. On the other hand, the gap between the power source lines around the periphery of the module is varied, depending on the kind of the module included in a semiconductor chip, and therefore it is not constant. Therefore, when the gap between the power source lines included in the module is different from that between the power source lines around the periphery of the module, guiding portions as shown by the elliptical portion in FIG. 17 are necessary in order to connect these power source lines. That is to say, it is necessary to design the guiding portions in accordance with the gap between the power source lines of the module.
In order to solve this problem, a semiconductor device as shown in FIG. 18 is presented. FIG. 18 is a diagram showing the configuration of a semiconductor device including a memory circuit. Hereinafter, a circuit design using the semiconductor device as shown in FIG. 18 as the module will be described.
The semiconductor device shown in FIG. 18 includes a memory circuit 1005, a fourth layer VSS line (hereinafter, referred to as “M4VSS line”) 1041, a fourth layer VDD line (hereinafter, referred to as “M4VDD line”) 1042, a third layer VDD power source line (hereinafter, referred to as “M3VDD line”) 1043, and a third layer VSS power source line (hereinafter, referred to as “M3VSS line”) 1044. The memory circuit 1005 is formed from the first to the fourth layers. The M4VSS line 1041, the M4VDD line 1042, the M3VDD line 1043 and the M3VSS line 1044 are formed in the third and the fourth layers, and supply a power source voltage VDD and a ground voltage VSS. That is to say, the semiconductor device shown in FIG. 18 is a circuit in which a portion from the first layer to the fourth layer is designed. The voltages supplied from the M4VSS line 1041, the M4VDD line 1042, the M3VDD line 1043 and the M3VSS line 1044 are supplied to the memory circuit 1005 through the lines (not shown) in the third layer and the layers beneath.
In the circuit design in which the semiconductor device shown in FIG. 18 is used as the module, semiconductor devices, which are the modules, are arranged in a semiconductor chip. Thereafter, power source lines in the fifth and sixth layers are arranged. Thus, the semiconductor chip 1000 as shown in FIG. 19 is completed. In the semiconductor device shown in FIG. 18, power source lines extending in the horizontal direction and the vertical direction are arranged in a portion around the periphery of the memory circuit 1005 in the third and fourth layers. Therefore, the power source lines in the fifth and sixth layers extending in the horizontal direction cross the power source lines in the third and fourth layers extending in the vertical direction, even if the gap between the power source lines is changed. Similarly, the power source lines in the fifth and sixth layers extending in the vertical direction cross the power source lines in the third and fourth layers extending in the horizontal direction, even if the gap between the power source lines is changed. Consequently, it is not necessary to design the power source lines in the fifth and sixth layers in accordance with the power source lines in the semiconductor device that is the module.
However, in the semiconductor device shown in FIG. 18, the power source lines in the third and fourth layers are arranged around the periphery of the memory circuit 1005, and therefore, the chip area of the semiconductor device is increased. To cope with this problem, it can be conceived to arrange the power source lines in the third and fourth layers above the memory circuit 1005, as shown in FIG. 20. However, the power source lines in the third and fourth layers cannot be arranged above the memory circuit 1005 for the following reason.
FIG. 21 is a block diagram showing the configuration of the memory circuit 1005. The memory circuit 1005 shown in FIG. 21 includes a memory cell area 1050, a data input/output portion 1051, a row decoder portion 1052, and a control portion 1053. In the data input/output portion 1051, the third layer VSS line and the third layer VDD line extending in the row direction shown by an arrow in FIG. 21 are present. In the row decoder portion 1052, the third layer VSS line and the third layer VDD line extending in the column direction shown by an arrow in FIG. 21 are present. In order to connect the power source lines in the memory circuit 1005 and the power source lines around the periphery of the memory circuit 1005, a connection as shown in FIG. 22 has to be performed. Hereinafter, a method for connecting these power source lines will be described with reference to FIG. 22. FIG. 22 is a diagram showing an enlarged portion α in FIG. 21.
In FIG. 22, a M4VSS line 1041 extending in the row direction and a M3VSS line 1066 extending in the column direction are connected via contacts. The M3VSS line 1066 extending in the column direction and a M4VSS line 1064 extending in the column direction are connected via contacts. The M4VSS line 1064 extending in the column direction and a M3VSS line 1062 extending in the row direction are connected via contacts. Thus, a ground voltage VSS is supplied from the M4VSS line 1041 to the M3VSS line 1062.
Similarly, a M4VDD line 1042 extending in the row direction and a M3VDD line 1065 extending in the column direction are connected via contacts. The M3VDD line 1065 extending in the column direction and a M4VDD line 1063 extending in the column direction are connected via contacts. The M4VDD line 1063 extending in the column direction and a M3VDD line 1061 extending in the row direction are connected via contacts. Thus, a power source voltage VDD is supplied from the M4VDD line 1042 to the M3VDD line 1061.
In order to supply the ground voltage VSS of the M4VSS line 1041 disposed outside the M4VDD line 1042 to the M3VSS line 1062 in the memory circuit 1005, the M3VSS line 1066 for extending below the M4VDD line 1042 is necessary. The M3VSS line 1066 is formed in the third layer, which is the same layer as the M3VDD line 1061 and the M3VSS line 1062 in the memory circuit 1005. As a result, as shown in FIG. 20, when the M4VSS line 1041 and the M4VDD line 1042 are arranged above the memory circuit 1005 in order to reduce the size of the semiconductor device, the M3VSS line 1066 cannot be formed.